1. Field of the Invention
The present invention relates to a buffer memory control system in a data processing apparatus. The system according to the present invention is applicable to a data processing system including a main memory and a central processing unit having a buffer memory for storing a copy of a portion of the information stored in the main memory, wherein speed-up of the access process to the buffer memory is needed when executing an immediate instruction.
2. Description of the Related Art
A buffer memory control system for executing a so-called immediate instruction is known (see Japanese Unexamined Patent Publication No. 60-123944). The immediate instruction performs a fetch operation, a store operation, or a so-called fetch and store operation (hereinafter referred to as FCH and ST). The FCH and ST performs, successively, a read out operation from and write in operation to the same address of the main memory.
In general, in a data processing system, a buffer memory is provided in a central processing unit, and data obtained by fetching (reading) data from a main memory of the central processing unit is stored in the buffer memory. The buffer memory has a smaller capacity but a shorter access time than the main memory. In the subsequent memory fetching, when the desired data is stored in the buffer memory, memory accessing is carried out to the buffer memory. When the desired data is not stored in the buffer memory, one block of data including the desired data is moved-in from the main memory to the buffer memory, and the buffer memory is then accessed to execute an instruction, thus allowing faster memory access.
In such a data processing system having a buffer memory, when a read out operation and write in operation are to be successively effected at the same address of the main memory, if the data at the same address is not stored in the buffer memory, one block (for example, 64 bytes) of data desired is moved-in (transferred) from the main memory to the buffer memory. The one block of data includes n subblocks, where n is a positive integer. The n subblocks are moved-in to the buffer memory one by one. The first subblock includes the desired data. Therefore, during the above mentioned move-in operation, the operand data (for example, the heading or the first X bytes) necessary for executing the above-mentioned immediate instruction is registered at an earlier stage in the buffer memory.
Conventionally, the execution of the immediate instruction is effected only after the move-in operation of one block is fully completed.
However, in view of the before mentioned circumstances, if the above-mentioned immediate instruction could be executed on the data during the move-in operation, the immediate instruction could be effected at an even earlier stage.